The present application relates to semiconductor device fabrication, and more particularly, to a method of forming a source contact and a drain contact (collectively referred to hereinafter as source/drain contacts) with reduced contact capacitance.
Field Effect Transistors (FETs) are essential components of all modern electronic products. FETs may include a semiconductor substrate containing a source region and a drain region spaced apart by a channel region on which a gate electrode may be formed. By applying voltage to the gate electrode, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
To allow current to flow between a source region and a drain region (collectively referred to as source/drain regions), electrical contacts need to be formed on the source/drain regions. The source/drain contacts may be formed by etching contact holes in a dielectric layer and filling the contact holes with a conductive material such as a metal. Source/drain contact resistance in a FET is proportional to the size of the contact areas. It is desirable to provide larger contact areas between the bottom of the contacts and the source/drain regions to reduce contact resistance therebetween. The larger contact areas for source/drain contacts may be achieved by forming larger size contact holes. However, a greater amount of conductive material that is needed to fill in the larger size contact holes can result in increased contact capacitance, which tends to impair overall device performance. Therefore, there remains a need to reduce the contact capacitance for source/drain contacts while maintaining low contact resistance.